IT 420 Spring 2018 Homework 3 Solutions

IT 420

Spring 2018

Homework 3 Solutions

1. Answer the following questions concerning error detection:

• In cyclic redundancy checking, what is the CRC?

1. the divisor b.  the quotient                        c.  the dividend           d.  the remainder

• A CRC is 6 bits long. How long is the divisor?

1. 5 bits b.  6 bits                      c.  7 bits                       d.  cannot be determined

• Which error detection method cannot always detect a multi-bit error?

1. single bit parity check b. checksum
2. CRC d.  all of the above can detect a multi-bit error

1.4  The checksum for 500 bytes of data is 16 bits long. Assuming the same algorithm is

used, how long will the checksum be for 1000 bytes of data?

1. 160 bits b.  32 bits        c. 16 bits          d. cannot be determined

            1.5  Assume we are calculating one checksum on two data items, A and B.  Instead of

            sending item A and then item B, we send item B and then item A.  Can the checksum detect

 this error?

1. yes              b.  no

1.6  The CRC for 500 bytes of data is 16 bits long. Assuming the same divisor is used, how

 long will the CRC be for 1000 bytes of data?

1. 160 bits b.  32 bits        c. 16 bits          d. cannot be determined

1. Assume 4-bit wide units of data.  Calculate the checksum for 1101 1001

1 1 0 1

1 0 0 1

         1 0 1 1 0

                  + 1

            0 1 1 1

            Checksum = 1 0 0 0

1. Assume a bit sequence of 101110 and a divisor of 1001. 

1. Generate the CRC

           1001  101110000

                     1001

                      0101

                      0000

                        1010 

                        1001

                         0110

                         0000

                          1100

                          1001

                            1010

                            1001

                              011                        CRC = 011     

1. Check the CRC

           1001  101110011

                     1001

                      0101

                      0000

                        1010 

                        1001

                        0110

                         0000

                          1101

                          1001

                            1001

                            1001

                              000                        CRC checks correctly 

1. A CRC polynomial is x⁴ + x + 1.  What is the divisor?

1x⁴ + 0x³ + 0x² + 1x¹ + 1x⁰

1 0 0 1 1

1. What kind of modulation or keying is shown below?  All three graphs together describe one modulation or keying method:  the top graph is the carrier wave, the middle graph is the data, and the bottom graph is the output signal.

            Amplitude Modulation

1. Draw constellation diagrams for:

1. 8-PSK

1. 8-QAM with at least two amplitudes

1. If you are using 128-QAM, how many bits does each point on the constellation diagram represent?

# bits = log₂ (128)

# bits = 7

1. Answer the following questions:

7.1  What characteristic of the carrier wave is changed to represent the data in ASK?

1. amplitude               b.  frequency               c.  phase                d.  period

7.2  What converts analog data to an analog signal?

1. multiplexing           b.  PCM           c. analog modulation        d.  keying

7.3  What kind of keying changes only the frequency of a carrier wave to represent data?

1. FM              b.  FSK            c. PSK                              d.  QAM

7.4  In what kind of multiplexing does each sender use all of the bandwidth of the link for a limited amount of time?

1. FDM   TDM          c. both of these                 d.  neither of these

    7.5  What scheme multiplexes analog signals?

1. a. FDM               TDM          c.  both of these                d.  neither of these

1. A single voice channel occupies a bandwidth of 4KHz. We need to multiplex 10 voice channels together using FDM and guard bands of 500 Hz.  What is the minimum bandwidth of the output of the multiplexer?

            BW_output = (10 * BW_channel) + (9 * BW_guard_band)

                            =   (10 * 4 KHz) + (9 * .5 KHz)

                            =   40 KHz + 4.5 MHz

                            =   44.5 KHz

1. Design a hierarchical TDM system to multiplex 8 channels, each with a 2 Mbps bandwidth, together.  Assume each multiplexer can combine, at most, 3 channels.  Sketch your design, showing the minimum bit rate of the output from the last-stage multiplexer.

1. Answer the following questions concerning network performance:

11.1  What is queuing delay?

1. The time required for a signal to travel across a transmission medium
2. The time needed to obtain access to a transmission medium
3. The time a packet spends waiting to be processed by a router
4. The time required for a server to respond to a request

   11.2  What is total delay?

1. the percentage of the network capacity being used
2. the time between when the first bit of a message is sent and when it is received
3. rate at which bits are transferred between a sender and receiver
4. change in delay

      11.3  What is goodput?

1. The total round-trip delay
2. The channel capacity of a single channel calculated using Nyquist’s or Shannon’s

                    formula

1. Amount of data transferred per unit time
2. Change in delay

     11.4  Change in delay is

1. throughput              b.  quality of service                c.  latency                    d.  jitter

12. Two hosts are separated by 4000 meters. Propagation speed in the link is 2x10⁸m/sec. What is the propagation delay?

Prop Delay = d / s

                    = 4000 m / 2 x 10⁸ m/sec

                   = 0.00002 sec = 20 µsec

1. A user downloads a 1000 Mbyte file in 2 seconds.  What is the average throughput in Mbits per second? 

      1000 Mbytes * 8 bits = 8000 Mbits

                                              byte

                  throughput = data size / time

                                     = 8000 Mbits / 2 sec

                                     = 4000 Mbps

1. What is the round-trip delay for a packet that passes through 3 routers on the way to the server and 3 routers on the way back?  Assume each router has a queuing delay of 2µsec,  each router has a switching delay of 1µsec, and the server delay is 50µsec. Neglect propagation and access delays.

Total delay = 6(2µsec +1µsec)  + 50µsec

                    = 68 µsec

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