MONASH UNIVERSITY Department of Electrical and Computer Systems Engineering ECE2072 ASSIGNMENT
Design a counter that produces an output every clock cycle. The output sequence that each student downloads from Moodle contains 18 Binary Coded Decimal (BCD) digits that are unique to each student. Let’s call these output values V0, V1, V2, .. V17. The count sequence wraps around from V17 back to V0. Here is the normal count sequence:
V0 V1 V2 V3 V4 V5 …V17 V0 V1 V2 V3 V4 V5 ….
There are additional inputs with these properties:
Design your counter using two modules. Module CounterSkipReverse implements the state sequence of the counter in sequential logic. The module StateToCountSequence is a combinational logic circuit that maps the state to your BCD V output. Since your unique BCD V sequence necessarily contains repeated digits (there are 18 in the sequence) the BCD output cannot act as the state of the counter, as often occurs with conventional counters. The design challenge here is to work out what state representation is appropriate.
Implement your design with a minimum number of flip-flops using Verilog compiled with Quartus with the standard project settings for a DE2 board. See the assignment FAQ on Moodle for settings that may be required to ensure a minimum number of flipflops are compiled when a FSM is detected in your code by Quartus.
Download from Moodle your Verilog template file named assignID.v that defines your count sequence V0 V1 V2 V3 V4 V5 …V17 . Note that ID in assignID.v is your 8 digit ID number. This particular file must be used for your HDL code to solve the above counter problem. Complete the modules CounterSkipReverse, StateToCountSequence and CompleteCounter. The file assignID.v must not be shared with, or shown to anyone else. Do not delete lines in this file since this may invalidate your answer during a preliminary automatic compilation, marking, plagiarism and collusion checking phase. Manual marking and checking will be used after this. Download a new copy from Moodle if you accidently delete lines.
In your assignID.v file complete the testbench module AssignmentTestBench that enables ModelSim to check the correct functionality of your HDL design. Ensure that you test every transition from every valid state of your circuit. Since we have a reset action, we are not testing for self-starting here. Include up to four screen captures from ModelSim showing the testbench simulation with inputs, outputs and state of your design. Use appropriate display options to maximise readability.
Minimise the number of Logic Cells that your design requires after a synthesis compilation in Quartus with DE2 board settings. This will involve exploring different implementation strategies, checking them with your testbench and synthesising them in Quartus. Include a screen capture of Quartus that clearly shows the number of Logic
Cells and “registers” (these are really flip-flops) after compilation for each module.
This screen capture must also show the time and date displayed on your computer. Here is an example (ignore the numbers since they are not applicable to your assignment):
Provide a photo of a neat, clear, hand drawn sketch of a synthesised representation of your Verilog design using the following logic components only:
Show the signal names and the number of bits per wire that match your Verilog. See Problem Sheet 3 solution to problem 5.4 for an example. Sign and date this diagram in the bottom right corner in your own handwriting. By submitting this, you are acknowledging that this is your own work and not copied from others or shared with others.
A marking rubric will be released a week before the Moodle submission date. It will include marks allocated to the Good Style Guide below.
Follow these guidelines when writing Verilog:
rather than rely on order:
DFlipflop dff1(clk, rst, data, out);
rather than working with individual flip-flop instantiations and Boolean expressions for each D input.
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