And the register overhead stands for approximately the clock period



Section 7.1  297  
7.1 








Figure 7.1 shows a block diagram of a generic finite state machine (FSM) that con  






Inputs 


LOGIC  
Current State  Registers  
Q 
Figure 7.1 Block diagram of a finite state machine using positive edgetriggered registers.
This chapter discusses the CMOS implementation of the most important sequential building blocks. A variety of choices in sequential primitives and clocking methodologies exist; making the correct selection is getting increasingly important in modern digital circuits, and can have a great impact on performance, power, and/or design complexity. Before embarking on a detailed discussion on the various design options, a revision of the design metrics, and a classification of the sequential elements is necessary.



298  DESIGNING SEQUENTIAL LOGIC CIRCUITS  
CLK  t  Register  
tsu  thold  D  
D 

t 


tcq  Figure 7.2 Definition of setup  
Q  t  
Given the timing information for the registers and the combination logic, some systemlevel timing constraints can be derived. Assume that the worstcase propagation delay of the logic equals tplogic, while its minimum delay (also called the contamination delay) is tcd. The minimum clock period T, required for proper operation of the sequential circuit is given by
T  ≥  tcq  +  tp  logic  +  

tcdregister  + tcdlogic  ≥ 

where tcdregister is the minimum propagation delay (or contamination delay) of the register.
1 (or when the clocks at different registers are somewhat out of phase due to clock skew, as will be discussed in a later Chapter)