And the register overhead stands for approximately the clock period

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	Section 7.1			297
	7.1	Introduction
	Combinational logic circuits, described earlier, have the property that the output of a logic
	preceding input values. In other words, a sequential circuit remembers some of the past
	history of the system—it has memory.
	Figure 7.1 shows a block diagram of a generic finite state machine (FSM) that con-
	State and the current Inputs and is fed to the inputs of registers. On the rising edge of the
	clock, the Next State bits are copied to the outputs of the registers (after some propagation
	input).
	Inputs			COMBINATIONAL
	LOGIC
	Current State			Registers
	Q

Figure 7.1 Block diagram of a finite state machine using positive edge-triggered registers.

This chapter discusses the CMOS implementation of the most important sequential building blocks. A variety of choices in sequential primitives and clocking methodologies exist; making the correct selection is getting increasingly important in modern digital cir-cuits, and can have a great impact on performance, power, and/or design complexity. Before embarking on a detailed discussion on the various design options, a revision of the design metrics, and a classification of the sequential elements is necessary.

	chapter7.fm Page 298 Friday, January 18, 2002 9:09 AM
	298	DESIGNING SEQUENTIAL LOGIC CIRCUITS
	CLK				t				Register
	tsu			thold	D
	D		DATA STABLE		t				CLK
	tc-q					Figure 7.2 Definition of set-up
	Q						t

Given the timing information for the registers and the combination logic, some sys-tem-level timing constraints can be derived. Assume that the worst-case propagation delay of the logic equals tplogic, while its minimum delay (also called the contamination delay) is tcd. The minimum clock period T, required for proper operation of the sequential circuit is given by

	T	≥	tc-q	+	tp	logic	+
	tcdregister			+ tcdlogic			≥	thold

where tcdregister is the minimum propagation delay (or contamination delay) of the register.

1 (or when the clocks at different registers are somewhat out of phase due to clock skew, as will be discussed in a later Chapter)