Can verify that the circuit figure implements the truthtable truth table
616  VS 

a n d  p o w e r  i n  d i g i t a l  

VS  C  
A 




B  
= 0.25 × (3 × 106) × (425 × 106) × (30 × 10−15) × 1.52 
B 




CMOS NAND Gate  

Notice that pulldown circuit comprising two seriesconnected NFETs is the



B  B  A  C  





¯f = NOTf. 

11.5 CMOS Logic 





f (A, B, C) = (A + B)C  
= (AB) C  
= AB + C  
= AB + C. 
An application of the ideas in Figure 11.26 leads to the circuit in Figure 11.27. We can verify that the circuit indeed correctly implements the logic by developing its truth table and comparing it to that of f.
I1  f 

C  VS  Out  

I2  A  
IN 
B C
FIGURE 11.27 CMOS FIGURE 11.26 CMOS configuration to implement the logic function f. implementation of f(A, B, C) = (A + B)C.