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# Can verify that the circuit figure implements the truthtable truth table  616 VS

C H A P T E R

a n d p o w e r i n d i g i t a l
VS C
A

the dynamic power consumed by the entire chip as

(Fraction Switching) × (#Gates) × fCLV2

B
= 0.25 × (3 × 106) × (425 × 106) × (30 × 10−15) × 1.52
B

nology? Let us look at a few examples and then generalize to arbitrary logic

functions. We have already seen one example

CMOS NAND Gate

Notice that pulldown circuit comprising two series-connected NFETs is the

 a b 1 1 1 1 0

table for a NOR gate as shown in Table 11.2.

The two pulldown NFETs are connected in parallel as in the corresponding NMOS implementation. The PFET pullups are series connected to form the

B B A C

interested in implementing the logic function f, the NFET pulldown network is

designed so it offers a short circuit when f is FALSE and an open circuit when

¯f = NOTf.  11.5 CMOS Logic

C H A P T E R

 c 1 0 0

Let us construct a CMOS circuit for the function

f is on. Let us derive an expression for¯f:
TABLE 11.2 Truth table.

f (A, B, C) = (A + B)C
= (AB) C
= AB + C
= AB + C.

An application of the ideas in Figure 11.26 leads to the circuit in Figure 11.27. We can verify that the circuit indeed correctly implements the logic by developing its truth table and comparing it to that of f.

I1 f

VS

C VS
Out
I2 A
IN

B C

FIGURE 11.27 CMOS FIGURE 11.26 CMOS configuration to implement the logic function f. implementation of f(A, B, C) = (A + B)C.

How It Works      