Further confirm the assumed robust-ness the gate

	chapter5.fm Page 187 Friday, January 18, 2002 9:01 AM
	Section 5.3										187
	2.5								gain	0 -10 -2 -4
	2
	1.5
	Vout(V)
	1
	0.5
	0
			0.5		1	1.5	2	2.5
	Vin (V)					(a)		Vin (V)			(b)
	Figure 5.10 = 2.5 V).		Simulated Voltage Transfer Characteristic (a) and voltage gain (b) of CMOS inverter (0.25 ∝m CMOS, VDD

	Problem 5.2 Inverter noise margins for long-channel devices
	Derive expressions for the gain and noise margins assuming that PMOS and NMOS are
	long-channel devices (or that the supply voltage is low), so that velocity saturation does
	not occur.
	5.3.3

While we design a gate for nominal operation conditions and typical device parameters, we should always be aware that the actual operating temperature might very over a large range, and that the device parameters after fabrication probably will deviate from the nom-inal values we used in our design optimization process. Fortunately, the dc-characteristics of the static CMOS inverter turn out to be rather insensitive to these variations, and the gate remains functional over a wide range of operating conditions. This already became apparent in Figure 5.7, which shows that variations in the device sizes have only a minor impact on the switching threshold of the inverter. To further confirm the assumed robust-ness of the gate, we have re-simulated the voltage transfer characteristic by replacing the nominal devices by their worst- or best-case incarnations. Two corner-cases are plotted in Figure 5.11: a better-than-expected NMOS combined with an inferior PMOS, and the opposite scenario. Comparing the resulting curves with the nominal response shows that the variations mostly cause a shift in the switching threshold, but that the operation of the

	188	THE CMOS INVERTER	Chapter 5

gate is by no means affected. This robust behavior that ensures functionality of the gate over a wide range of conditions has contributed in a big way to the popularity of the static CMOS gate.

	ages are virtually kept constant. The reader probably wonders about the impact of this
	trend on the integrity parameters of the CMOS inverter. Do inverters keep on working
	ply voltage! Note that for a fixed transistor ratio r,VM is approximately proportional to VDD. Plotting the (normalized) VTC for different supply voltages not only confirms this conjecture, but even shows that the inverter is well and alive for supply voltages close to
	the threshold voltage of the composing transistors (Figure 5.12a). At a voltage of 0.5 V —
	arguments come to mind:
	•	In the following sections, we will learn that reducing the supply voltage indiscrimi-
	•
	ages become comparable.
	•	Scaling the supply voltage means reducing the signal swing. While this typically