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Large numbers holes enter the base region

Voltage, V
Forward Reverse

+V0 12.14 Semiconductor Devices S-95
0

junction having the voltage–current

V0

characteristics shown in Figure 12.20.

IF

Time

0 IR
(b)

THE TRANSISTOR

Junction 1 Junction 2

Forward-biasing voltage

+ Emitter Base

Collector

p n p

Input
voltage

Load +

including input and

characteristics showing

0.1
voltage
Input
(mV)

10 voltage
Output
(mV)

Time

Time
S-96
p-Type

+

FIGURE 12.23 For a junction transistor

p-Type n-Type
+ +
+
+ + +
+ + + +
+

potential is applied and (b) with appropriate

+ + +
+ +

+

+
+ Base + + Junction 2

Emitter

Collector

+ + + + + +
+
+
+ + +
+ + +
+
+

its attendant circuitry. A very thin n-type base region is sandwiched in between p-type emitter and collector regions. The circuit that includes the emitter–base junction (junction 1) is forward biased, whereas a reverse bias voltage is applied across the base–collector junction (junction 2).

Figure 12.23 illustrates the mechanics of operation in terms of the motion of charge carriers. Since the emitter is p-type and junction 1 is forward biased, large numbers of holes enter the base region. These injected holes are minority carriers in the n-type base, and some will combine with the majority electrons. However, if the base is extremely narrow and the semiconducting materials have been properly prepared, most of these holes will be swept through the base without recombination, then across junction 2 and into the p-type collector. The holes now become a part of the emitter–collector circuit. A small increase in input voltage within the emitter–base circuit produces a large increase in current across junction 2. This large increase in collector current is also reflected by a large increase in voltage across the load resistor, which is also shown in the circuit (Figure 12.22). Thus, a voltage signal that passes through a junction transistor experiences amplification; this effect is also illustrated in Figure 12.22 by the two voltage–time plots.

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