The charge pump also forms low pass filter
86 J. Daniels et al.
To reduce area and power consumption, one can combine a coarse measurement with a finer measurement using e.g. a delay line [13]. For the coarse measurement, a counter counts the number of clock periods that fit the time interval to be measured. The residue, i.e. the distance between the nearest clock edge and the input edge is then measured using clock interpolation with a delay line or a similar architecture. In theory, the dynamic range of this kind of circuits can be arbitrarily high without influencing the size of the interpolation stage. Calibration of each stage is mandatory however to match the measured outputs of the stages with each other.
| Fig. 9 Multi-stage TDC [1] with a digital counter
(1), a coarse interpolation stage with a recycling DLL (2) and a fine interpolation stage with two parallel delay lines (3) |
|---|
A classic analog approach for Clock and Data Recovery is depicted in Fig. 10a. It uses an analog PLL [14] to synchronize a clock with the data, and uses this clock signal to resample the data. The PLL uses a phase detector (PD) which detects the phase difference between the input data and the clock signal. The PD typically generates an up and a down pulse of which their lengths are proportional to the phase error. These pulses drive a charge pump (CP) which converts the phase error into a current, charging or discharging a capacitance. The charge pump also forms a low pass filter, which stabilizes the loop. The resulting control voltage drives a voltage-controlled oscillator (VCO) towards phase lock.
| Time to Digital Conversion: An Alternative View on Synchronization | decision block | clkout | 87 | |||||
|---|---|---|---|---|---|---|---|---|
| up | lowpass filter | VCO | ||||||
| down | dataout | |||||||
|
TDC | ε |
|
DAC | VCO | decision block | clkout |
|---|---|---|---|---|---|---|---|
| dataout |
| TDC | ε | DCO | decision block | clkout | ||
|---|---|---|---|---|---|---|
| dataout |
Fig. 10 PLL-based CDR: (a) analog PLL, (b) PLL with a TDC as a digital phase detector, (c) All-Digital PLL
More digital approaches replace several or all of these blocks with digital ver-sions. Example in Fig. 10b the PD is replaced by a TDC which outputs the phase error as a digital value. The charge pump and low-pass filter are then replaced by a digital filter. Then a D/A Converter converts the result back to the analog control voltage for the VCO.
