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# The computed transient response the circuit plotted figure

chapter5.fm Page 197 Friday, January 18, 2002 9:01 AM

Section 5.4
197
2.5 Vin

Vout

2

out(V) 1.5
1
= tpLH 2 Figure 5.16

Simulated transient

V 1
0.5
0 0.5

1.5

response of the inverter of Figure
-0.5
x 10
tpHL

--------------13kΩ

1.5

⋅ 6.1fF =
tpLH =

4.5

⋅ 6.0fF =
tp = and =

The accuracy of this analysis is checked by performing a SPICE transient simulation on the circuit schematic, extracted from the layout of Figure 5.15. The computed transient response of the circuit is plotted in Figure 5.16, and determines the propagation delays to be 39.9 psec and 31.7 for the HL and LH transitions, respectively. The manual results are good considering the many simplifications made during their derivation. Notice especially the overshoots on the simulated output signals. These are caused by the gate-drain capacitancesof the inverter transistors, which couple the steep voltage step at the input node directly to the output before the transistors can even start to react to the changes at the input. These over-shoots clearly have a negative impact on the performance of the gate, and explain why the simulated delays are larger than the estimations.

chapter5.fm Page 198 Friday, January 18, 2002 9:01 AM

THE CMOS INVERTER Chapter 5
tpHL = 0.693 4---CLVDD IDSATn = 0.52

W L )nknVDSATn VDDVTnVDSATn 2 )

(5.21)

tpHL 0.52
(5.22)

This analysis is confirmed in Figure 5.17, which plots the propagation delay of the

inverter as a function of the supply voltage. It comes as no surprise that this curve is virtu-

tp(normalized)

1.5
3

2

3.5

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4

predicted by Eq. (5.21). Observe that this

equation is only valid when the devices are

Design Techniques

From the above, we deduce that the propagation delay of a gate can be minimized in the fol-lowing ways:

How It Works