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The pmos transistor displays reverse behavior

chapter5.fm Page 191 Friday, January 18, 2002 9:01 AM

Section 5.4

Gate-Drain Capacitance Cgd12

The lumped capacitor model now requires that this floating gate-drain capacitor be

replaced by a capacitance-to-ground. This is accomplished by taking the so-called Miller

large as the floating capacitance.

We use the following equation for the gate-drain capacitors: Cgd = 2 CGD0W (with CGD0 the overlap capacitance per unit width as used in the SPICE model). For an in-depth discussion of the Miller effect, please refer to textbooks such as Sedra and Smith ([Sedra87], p. 57).1

V Cgd1 Vout Vout
Vin M1 V


Figure 5.14 The Miller effect—A capacitor experiencing identical but opposite voltage swings at both

192 Ceq =



with Cj0 the junction capacitance per unit area under zero-bias conditions. An expression for Keq was derived in Eq. (3.11) and is repeated here for convenience

Keq = [ ( φ0 Vhigh )1 m ( φ0 Vlow )1 m

with φ0 the built-in junction potential and m the grading coefficient of the junction. Observe that the junction voltage is defined to be negative for reverse-biased junctions.

Example 5.3

inverter, this is the time-instance where Voutreaches 1.25 V, as the output voltage swing goes from rail to rail or equals 2.5 V. We, therefore, linearize the junction capacitance over the

interval {2.5 V, 1.25 V} for the high-to-low transition, and {0, 1.25 V} for the low-to-high

Bottom plate: Keq (m = 0.5, φ0 = 0.9) = 0.57,
Sidewall: Keqsw (m = 0.44, φ0 = 0.9) = 0.61

During the low-to-high transition, Vlow and Vhighequal 0 V and −1.25 V, respectively, resulting in higher values for Keq,

Bottom plate: Keq (m = 0.5, φ0 = 0.9) = 0.79,
Sidewall: Keqsw (m = 0.44, φ0 = 0.9) = 0.81

Using this approach, the junction capacitance can be replaced by a linear component and treated as any other device capacitance. The result of the linearization is a minor dis-tortion of the voltage waveforms. The logic delays are not significantly influenced by this simplification.

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